Host Interface (HI08)
HTX/HRX Bit Number: 23
0
DSP side
Host side
aa
bb
cc
Low Byte
Host bus address:
cc
$5
bb
$6
aa
$7
High Byte
(read/write last!)
Host 32-bit
internal register
xx
cc
bb
aa
Figure 6-4. HI08 Read and Write Operations in Little Endian Mode
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three store
(or load) byte operations, ensuring that the data byte at host bus address $7 is written last since
this causes the transfer of the data to the DSP-side HRX. However, the host bus controller may be
sophisticated enough that the host can transfer all bytes in a single operation (instruction). For
example, in the PowerPC MPC860 processor, the General-Purpose Controller Module (GPCM)
in the memory controller can be programmed so that the host can execute a single read (load
word, LDW) or write (store word, STW) instruction to the HI08 port and cause four byte
transfers to occur on the host bus. The 32-bit datum transfer shown in Figure 6-4 has byte data xx
written to HI08 address $4, byte aa to address $5, byte bb to address $6 and byte cc to address $7
(this assumes the 24-bit datum is contained in the lower 24 bits of the host’s 32-bit data register
as shown).
A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing the Host
Little Endian bit (ICR[5] = HLEND). Big Endian mode is depicted in Figure 6-5 .
HTX/HRX Register: 23
0
DSP side
Host side
aa
bb
cc
High Byte
Host bus address:
aa
$5
bb
$6
cc
$7
Low Byte
(read/write last!)
Host 32-bit
internal register
xx
aa
bb
cc
Figure 6-5. HI08 Read and Write Operations in Big Endian Mode
DSP56311 User’s Manual, Rev. 2
6-10
Freescale Semiconductor
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